Chapter 242 - Chapter 231: The Architecture of the Future

Chapter 231: The Architecture of the Future

1974–August 1976Gorakhpur Industrial Complex — ISMC Division and Shergill Computer Systems

(Guys there may be some historical errors bcoz last chapter i had wrote about semconductor was so ealry that claude has no memory and transport of memory consumes all credit and generate no chapter bcoz all credits gt wasted in reading memory,thats why i didnt write single chater abot that nt a single chapter abot s27 specially, so accept everything this chapter says pls for memory))

There were things Karan Shergill knew that he could not explain.

Not intuitions. He had been in this life long enough that the distinction between what he had reasoned and what he remembered from the life before had blurred at the edges into something that felt seamless. The knowledge was simply present: the knowledge of what computing would become, what it would cost and enable and transform, the specific trajectory of the technology across the decades he had watched it travel from a different vantage point. He had built Shergill Industries on mechanical and chemical and aerospace engineering for the first five years because those were the disciplines where Indian talent and Indian need intersected most visibly and most immediately. But the thing he had always known was coming — the thing he had been building toward since the first transistor came off the ISMC line in 1970 — was the age of silicon.

Not the age of silicon as the world understood it in 1974. Not the age of calculators and mainframes and the modest, sufficient, incremental progress of a technology finding its commercial footing.

He knew what silicon would become. He knew about the internet. He knew about the smartphone. He knew about GPS and satellite networks and the specific vulnerability of industrial infrastructure to software attack. He knew about cryptography and the arms race between encryption and the people trying to break it. He knew that the Cold War would eventually be fought as much with silicon as with missiles — perhaps more, because missiles destroyed and silicon controlled.

He could not explain any of this to the engineers he employed. He could only direct.

And there was one principle above all others that he had held from the first day of the ISMC project and would hold until the last: India would build everything itself.

Not as an ideological position, though the ideology was also correct. As a strategic calculation. The specific calculation that a country which depended on a foreign supplier for the tools to make its technology was a country that had chosen to be vulnerable at the most fundamental possible level. If ISMC needed a German stepper or an American photoresist or a Japanese vacuum system to fabricate chips, then ISMC's capability existed only at the pleasure of the country supplying that tool. And countries did not supply tools to other countries out of generosity. They supplied them because the supply served their interests. When the supply ceased to serve their interests, the supply stopped.

This was not a theoretical concern. Karan had watched, in the life he remembered, the specific consequences of technological dependency play out across decades. He had watched American export controls cut off Soviet semiconductor development at specific capability nodes. He had watched Japanese memory manufacturers absorb American chip companies during the 1980s technology race. He had watched China's attempts at semiconductor self-sufficiency in the 2010s and 2020s — the specific, catastrophic cost of trying to build indigenous capability after having spent two decades becoming dependent on foreign supply chains.

He had decided, before building the first wall of the ISMC facility, that India would not make that mistake. Every element of the semiconductor fabrication process — the lithography equipment, the chemistry, the materials, the software — would be Indian in design and Indian in manufacture. The initial capability would be worse than what could be purchased from a German or Japanese supplier. It would be worse for several years. And then it would be better, because it would be understood at every level by people who had built it, and because the understanding that came from building a thing was different in kind from the understanding that came from operating a thing you had purchased.

The direction, from August 1974 onward, was a word he never stopped using with Krishnaswami: faster.

Not faster in the sense of hurrying. Faster in the sense of compressing timelines that the world considered reasonable. The world considered three-micron semiconductor fabrication adequate in 1974. In 1976, ISMC was preparing to leave three microns behind, using equipment that no other country's engineers had designed, fabricated on tools that no other country had built, implementing processes that had been developed in-house from first principles.

The interferometric testing system — the measurement capability that allowed Ghosh to verify the wavefront error of the lens assembly — was built by an electronics engineer named Subramaniam who had come from the Indian Space Research Organisation's satellite payload calibration programme and who understood precisely the relationship between interferometric measurement and optical performance. The system used a stabilised helium-neon laser as the reference beam and a CCD camera array — fabricated at ISMC's own device laboratory — as the detector, producing a live fringe pattern that showed the deviation of the lens assembly's wavefront from a perfect sphere.

The first generation ISMC lithography system — the IPL-1, for Indian Projection Lithography — was completed in the spring of 1972. It used a mercury arc lamp emitting at 365 nanometres through a lens assembly with a numerical aperture of 0.35, projecting a ten-to-one demagnification of the mask pattern onto the wafer surface. The theoretical resolution limit was approximately 700 nanometres at this wavelength and NA — considerably better than the ten-micron specification.

Ghosh had designed conservatively. The ten-micron specification he had agreed to in 1970 was not the limit of what the IPL-1 could do. It was the limit he was confident he could guarantee. The actual performance was four microns.

When he told Karan, Karan said: "You gave yourself an extra two years."

Ghosh said: "I gave myself a specification I knew I could meet. What I produced was better than the specification. The better is not an accident. The better comes from building with precision beyond the requirement, because precision is what you have when something goes wrong and you need to understand why."

Karan had written this in his notebook.

By 1974, the ISMC fabrication line was running on the IPL-2, the second-generation lithography system that Ghosh's team had designed in 1972 and refined through 1973. The IPL-2 used a higher NA lens — 0.45 — and a more stable illumination uniformity system that had been the result of eighteen months of work on the mercury lamp's collection optics. The IPL-2 produced two-micron features reliably. Three-micron features at production yield.

The three-micron process node that had allowed the Brahma-16's production in late 1973 ran on the IPL-2.

And in October 1974 — 4 years from Ghosh's estimate in the October 1970 meeting — Ghosh came to Karan's office with a design document.

He set it on the desk.

He said: "The IPL-3. Deep ultraviolet. 248-nanometre wavelength. Fused silica lens elements. Designed for one-micron features."

Karan looked at the document.

He said: "The fused silica polishing."

Ghosh said: "Balakrishnan solved it. Not the way I thought he would. He developed a new polishing medium — a cerium oxide slurry with a specific particle size distribution that we control by our own synthesis process. The fused silica responds to this medium differently from how it responds to conventional optical polishing compounds. The surface produced is smoother by a factor of three."

"How long did it take him?" Karan said.

"Eight months," Ghosh said. "From the time I told him what we needed to the first production-quality fused silica element."

"And the light source?" Karan said.

The deep-UV light source problem had been one of the two hardest problems in the IPL-3 design. Mercury arc lamps had inadequate output at 248 nanometres. The conventional solution — excimer lasers — did not exist as commercially available products in 1974. They existed as laboratory devices.

Ghosh said: "The light source is the reason the IPL-3 took five years from our conversation rather than four. The mercury lamp's 248-nanometre output is too weak for production use — the exposure times would be prohibitively long. I spent two years trying to improve the collection efficiency of the mercury lamp's deep-UV output before concluding that I was approaching the physical limit."

He paused.

He said: "Then I spoke to Dr. Mehta."

Mehta — not the Akash-Net Mehta, but a different Dr. Mehta, Rajesh Mehta, a plasma physicist who had come to the ISMC research division from the Bhabha Atomic Research Centre in 1972 — had been working on plasma discharge physics for applications in the industrial gas processing equipment that the ISMC facility used for dry etching. He understood, in considerable depth, the physics of electrical discharge in gases.

Ghosh had asked him: is it possible to design a high-intensity UV source based on a plasma discharge in a krypton-fluoride gas mixture?

Mehta had said: in principle, yes. The krypton-fluoride excimer emission at 248 nanometres has been observed in laboratory discharges. Making it reliable, high-intensity, and repetition-rate capable — that is an engineering problem.

Ghosh had said: solve the engineering problem.

Mehta had spent fourteen months solving the engineering problem.

The ISMC Excimer Source Unit — the ESU-1 — was a sealed gas discharge tube, 60 centimetres long and 15 centimetres in diameter, containing a krypton-fluoride gas mixture at two atmospheres pressure, with electrode geometry designed by Mehta to produce a stable, homogeneous discharge across the full cross-section of the tube. Operated at 1,000 pulses per second, the ESU-1 produced an average power output at 248 nanometres that was twenty times the IPL-2's mercury lamp output at that wavelength.

Twenty times the output.

Which meant exposure times twenty times shorter.

Which meant wafer throughput twenty times higher for a given resolution.

Ghosh presented the IPL-3 design to Karan in October 1974 with the ESU-1 as its light source, the fused silica lens assembly as its optics, and a theoretical resolution of 600 nanometres with the designed NA of 0.52.

Karan had read the document.

He had said: "The theoretical resolution is 600 nanometres. The production process node target is one micron. You have 400 nanometres of engineering margin."

Ghosh had said: "Yes. I have designed more margin than I expect to need, because the first production experience with a new system always reveals constraints that the design analysis did not identify. The 400-nanometre margin exists so that when we find those constraints, we have room to address them without immediately being against the system's physical limit."

Karan had said: "The process chemistry."

This was the second hard problem. The photoresist — the light-sensitive chemical layer on the wafer surface — needed to respond efficiently at 248 nanometres. Conventional photoresists were designed for the 365-nanometre near-UV wavelength. At 248 nanometres, they absorbed too strongly, limiting the exposure depth and making the pattern transfer to the underlying film less accurate.

Ghosh had said: "That is Deshpande's problem."

Ashwin Deshpande was twenty-six years old, from Pune, three years from his doctorate at IIT Bombay where he had studied the photochemistry of aromatic compounds under ultraviolet irradiation. He had come to ISMC in January 1974, recruited specifically from Ghosh's description of what the IPL-3 would need.

The Chemistry That Made It Possible

Deshpande had been given a laboratory and a problem.

The problem, stated simply: design a photoresist that responds efficiently to 248-nanometre light and that produces the pattern resolution that the IPL-3's optics were capable of delivering.

Stated less simply: the problem required a complete departure from the chemistry of existing photoresists.

Conventional photoresists — the ones used on ISMC's IPL-1 and IPL-2 systems — worked through a direct photochemical reaction: ultraviolet photons split the photoactive compound in the resist, which changed its solubility in the developer solution. The reaction was one photon per chemical event. This was efficient enough at 365 nanometres. At 248 nanometres, where the photon flux from even the ESU-1 was lower than the mercury lamp's 365-nanometre output, the conventional chemistry's sensitivity was inadequate.

Deshpande's insight — arrived at in September 1974, after nine months of working through the resist chemistry problem from multiple angles — was the chemically amplified approach.

He described it to Ghosh and Krishnaswami in the meeting where he presented it:

"The problem with conventional resists is that one photon does one chemical event. If the light is weak, the rate of chemical events is slow, and either the exposure time is long or the contrast between exposed and unexposed areas is insufficient for good pattern transfer." He paused. "The solution is to make each photon do many chemical events. Not through a chain reaction in the explosive sense — through a catalytic mechanism. A single photon creates a catalyst molecule. The catalyst molecule then triggers a sequence of chemical reactions, potentially hundreds or thousands, before it is consumed. The amplification factor — the ratio of chemical events to photons — can be designed into the chemistry."

Krishnaswami said: "This is not a known resist chemistry."

Deshpande said: "No. The concept has been discussed in the photochemistry literature as a theoretical possibility. I am proposing to make it real."

Ghosh said: "What is the chemistry?"

Deshpande had spent the previous three weeks preparing this answer.

He said: "The photoactive compound generates a strong acid upon ultraviolet exposure. A single photon creates a single proton. The proton then catalytically cleaves protective groups from the polymer backbone of the resist. Each proton can cleave many protective groups before it is neutralised by the base additive that controls the amplification. The cleaved polymer is soluble in the developer. The uncleaved polymer is not. The selectivity — the difference in solubility between exposed and unexposed resist — is determined by the degree of deprotection, which is controlled by the proton concentration, which is controlled by the exposure dose." He paused. "The amplification factor is approximately one hundred to five hundred, depending on the base loading. One photon at 248 nanometres creates one proton, which cleaves between one hundred and five hundred protective groups."

He paused.

"The sensitivity is one hundred to five hundred times higher than conventional resist at the same wavelength," he said. "The exposure time is correspondingly shorter. At the ESU-1's output intensity, the exposure time is comparable to what we currently use with the IPL-2 at 365 nanometres."

Ghosh said: "Can you synthesise it?"

Deshpande said: "I need the polymer backbone. I need the protective groups. I need the photoacid generator. I need to understand the base loading required for the specific amplification factor that the process needs." He paused. "Four months to the first testable formulation."

"Three months," Krishnaswami said.

Deshpande looked at him.

"I know," Deshpande said. "Three months."

He had the first testable formulation ready in two months and three weeks.

The first formulation was not adequate — the dissolution contrast between exposed and unexposed resist was insufficient for the pattern fidelity the one-micron process required. The second formulation, which adjusted the acid generator's quantum yield and the protective group's lability, was better. The third formulation, which optimised the base loading to control the reaction front diffusion that was causing the pattern edges to blur, produced the resolution that the IPL-3's optics were capable of delivering.

The third formulation was completed in March 1975.

Every component of the third formulation — the polymer backbone, the protective groups, the photoacid generator, the base additive — was synthesised entirely within ISMC's chemistry division. Not a single component was purchased from a foreign supplier. The synthesis routes had been developed by Deshpande and his three-person team from first principles, guided by the structural requirements of the resist chemistry rather than by any existing recipe.

When Karan reviewed the chemistry programme in April 1975, he asked Deshpande the question that he asked about everything:

"Can someone recreate this resist chemistry from the published literature?"

Deshpande had thought about this for a moment.

He had said: "The concept of chemically amplified resists has been discussed in academic chemistry literature. Someone who understood the concept and had the relevant organic chemistry skills could arrive at a formulation similar to ours. The specific formulation — the precise combination of polymer backbone, protective group, photoacid generator, and base loading that we have optimised — that specific combination is ours. It would take an independent researcher two to three years to arrive at an equivalent through independent work."

"Two to three years from today," Karan had said.

"Yes," Deshpande had said.

"Or they could find out what we have done and use it," Karan had said.

Deshpande had looked at him.

"Yes," Deshpande had said.

This was the beginning of the document control system for the chemistry programme — the specific, comprehensive logging of every synthesis record, every formulation notebook, every test result, managed through the Chanakya database with access limited to the people who needed each piece for their work.

The IPL-3 Comes Online

The IPL-3 was completed in the autumn of 1975 and spent four months in the engineering evaluation phase — the period during which the system was operated under controlled conditions to map its actual performance, identify the points where it deviated from the design prediction, and correct those deviations before committing it to production use.

The evaluation was conducted by a team led by Ghosh himself, with Deshpande managing the resist chemistry evaluation in parallel.

The process of evaluating a new lithography system was a specific, meticulous exercise in measurement. The lens aberrations were characterised using the interferometric test setup. The illumination uniformity across the exposure field was mapped. The focus-exposure matrix was run — a grid of test wafers with systematically varied focus position and exposure dose, producing a map of how the pattern quality responded to the control parameters. The overlay accuracy — the precision with which the new pattern could be aligned to a previously printed pattern — was measured.

Each measurement produced a number. Each number either confirmed the design prediction or revealed a deviation that needed to be understood.

The most significant deviation in the IPL-3 evaluation was in the overlay accuracy. The design target was 50 nanometres. The measured performance was 180 nanometres — considerably worse than the target, and insufficient for the multi-layer process that the one-micron device fabrication required.

The investigation of the overlay error took three weeks and eventually identified the cause: thermal drift in the wafer stage during the exposure sequence. The stage — the precision mechanism that held the wafer and moved it to each exposure position — was warming slightly as the ESU-1 pulsed, and the thermal expansion of the stage was producing a systematic offset in the wafer position.

The stage temperature control system was redesigned by the mechanical engineering team. The new thermal management incorporated active temperature control — a heat exchanger coupled to the stage structure — that maintained the stage temperature stable to within one-tenth of a degree Celsius during operation.

With the thermal management upgrade, the overlay accuracy improved to 47 nanometres.

The IPL-3 was accepted for production use in February 1976.

The first production wafers on the one-micron process ran in March 1976.

The yield — the fraction of working dies per wafer — was 28 percent. Below the 40 percent target. Investigation identified two yield-limiting mechanisms: a photoresist coating defect rate that was higher than acceptable, and a dry etch uniformity issue in the critical gate oxide patterning step. Both were addressed through process refinements in April and May. By June, the yield was 43 percent. Still below the eventual 60 percent target, but adequate for the Brahma-32 first silicon fabrication.

The first Brahma-32 silicon was produced in July 1976.

When Seshadri held the first packaged Brahma-32 device — the ceramic package with its array of pins, the chip inside it representing 180,000 transistors and the most complex circuit ever designed in India — he said nothing for a long time.

He was standing in the testing area, and Ghosh was beside him, and Deshpande was at the test station running the validation suite.

Ghosh said: "The IPL-3. The ESU-1. The chemically amplified resist. All of it ours."

Seshadri said: "All of it."

"Nobody else has this," Ghosh said. Not with pride in the boastful sense. With the specific quality of a person stating a fact that he had understood for two years and that had not changed and that, now that the device existed, was no longer an engineering prediction but a demonstrated reality.

"Nobody else has this," Seshadri confirmed.

The test programme showed 92 percent validation pass on the first batch.

Deshpande called Krishnaswami.

Krishnaswami called Karan.

The Process Node Imperative

The most important single decision of the ISMC's first six years had not been a product decision. It had been a numbers decision.

In 1970, when ISMC's first fabrication facility came online, the process node was ten microns. By the international standard — by what the American and Japanese companies were doing — this was competitive for 1970. By 1973, it was dated. Intel was at four microns. Japan was at the same level.

ISMC had reached four microns in 1971 and three microns in late 1972, driven by the process development team's systematic work and the improving capability of the IPL-1 and IPL-2 systems. By 1973, ISMC was at three microns. By the international standard, they were on pace.

Karan looked at the pace and made a decision.

He told Seshadri in January 1974: "I want one micron by 1976."

Seshadri looked at him.

He said: "Intel's roadmap targets one and a half microns by 1977 at the earliest. One micron is their 1980 target."

Karan said: "I know."

Seshadri said: "You are asking me to be four years ahead of the most advanced semiconductor company in the world."

Karan said: "Yes."

Seshadri said: "The Ghosh optics programme. The IPL-3."

"Yes," Karan said.

"Ghosh has been designing for this since 1970," Seshadri said.

"Yes," Karan said.

Seshadri processed this for a moment — the specific understanding of a process engineer realizing that the programme he was being told to execute had been in preparation for five years before he was being told to execute it.

He said: "And the resist chemistry."

"Deshpande," Karan said.

"Deshpande has been hired for this specific problem," Seshadri said.

"Yes," Karan said.

Seshadri looked at the plan.

He said: "Two and a half years."

Karan said: "Two and a half years."

Seshadri said: "The yield at one micron. The first time we run a new process, the yield is always low. Two and a half years does not give me time to develop the process to production yield and fabricate the Brahma-32."

"I know," Karan said. "We start the Brahma-32 architecture work now. The first silicon is the validation. The production yield develops in parallel. We are not waiting for sixty percent yield before we start the architecture. We are building the architecture that is ready when the yield is ready."

"That is an unusual approach," Seshadri said.

"It is the correct approach," Karan said. "If we wait for the process before we start the architecture, we add another eighteen months. If we develop them in parallel, the process and the architecture are both ready at the same time."

Seshadri thought about the risks.

He said: "The risk is that the architecture is designed for a process capability that we do not achieve. If the one-micron process cannot reach the transistor density required for the Brahma-32, the architecture needs to be redesigned for whatever density we can achieve."

"Yes," Karan said. "Design the architecture with a transistor budget that is conservative. Design it to work at 120,000 transistors if we need to, while targeting 180,000. The capability above the minimum is features, not the minimum."

Seshadri understood this.

"The architecture team needs to work with a process specification that includes uncertainty bounds," he said.

"Tell Malhotra," Karan said. "He understands uncertainty bounds."

The decision had been made. The specific architecture of the decision — the optical programme, the chemistry programme, the process development programme, the architecture programme, all running simultaneously and connected at specific points — was the reason ISMC was where it was in August 1976.

Not luck. Not a single breakthrough. The sustained application of a plan that had been running for seven years.

The Security Architecture

In 1973, ISMC had no security programme worth the name.

There was a perimeter fence. There were guards at the gates. There was a standard industrial facility's understanding of security, which was approximately: don't let unauthorised people walk in the front door.

Karan had replaced this with something considerably more serious, for a reason he had expressed to very few people.

He said to Krishnaswami in October 1973: "I want to describe what I believe will happen if this facility develops the capabilities we are planning."

Krishnaswami said: "Go ahead."

Karan said: "A domestic semiconductor capability at the level we are targeting is not invisible. In the short term, the Americans, the Soviets, and the British do not know what we are doing because they are not paying attention. At some point they will pay attention. When they pay attention — specifically when their intelligence services assess what we have — we will receive visitors we did not invite."

Krishnaswami said: "What kind of visitors?"

Karan said: "Intelligence operatives. Some as commercial visitors. Some as research collaborators. Some as employees. The entry method is irrelevant. What they are doing is acquiring information about our processes, our designs, our capabilities, our personnel. The information goes to their principals. Their principals use it to calibrate their own programmes and eventually to make decisions about whether what we have built serves their interests or threatens them."

Krishnaswami said: "This is a theoretical concern."

Karan said: "It is not theoretical. It is a timeline question. We are safe for approximately two years. After that, we will be of sufficient interest to attract professional attention. And I want to be very specific about what I am protecting."

He said: "I am not protecting against a competitor learning our business model or our product roadmap. I am protecting against a foreign intelligence service learning the specific technical capabilities of the IPL-3 and the chemically amplified resist chemistry and the Brahma architecture. If those capabilities become known, two things happen. First, our advantage in each domain is eliminated — a foreign laboratory with a year's head start on the problem and our specific technical approach can replicate our results faster than they would have without our information. Second, and more serious: the country that has our technical information may decide that India having it is contrary to their interests and will take steps to prevent India from maintaining it. Not through competition. Through other means."

Krishnaswami was quiet for a long time.

He said: "You are describing a scenario where a foreign government actively interferes with ISMC."

"Yes," Karan said.

Krishnaswami said: "On what basis do you believe this is a real possibility?"

Karan said: "On the basis that the United States government has a specific, documented history of using export controls and other mechanisms to prevent the Soviet Union from acquiring advanced semiconductor capability. The Soviets have a documented history of using intelligence operations to acquire American semiconductor designs and process knowledge. Both of these are documented facts." He paused. "India is not the Soviet Union. But India with an advanced indigenous semiconductor capability is a country that has reduced a specific category of strategic leverage that the major powers can exercise over it. Removing that leverage is not in the major powers' interest." He paused. "I am not being paranoid. I am being precise."

The Internal Security Division was established in January 1974 under R.D. Nair, a retired Intelligence Bureau officer from Kerala who had spent twenty years in technical intelligence and who understood both the threat landscape and the specific nature of what needed protecting.

In April 1975, a man presenting himself as an engineer from a West German industrial instrumentation company visited ISMC's commercial sales office requesting a meeting about potential purchasing of custom analog circuits. His papers were entirely authentic. His references were entirely authentic. His company was entirely real.

Nair's team — which by April 1975 had established a baseline monitoring protocol for all facility visitors — had caught the deviation in his behaviour that identified him.

The technical competence assessment: a brief conversation with one of ISMC's commercial engineers, designed to establish whether the visitor's claimed technical background was consistent with his claimed purpose. The visitor's questions about analog circuit specifications were inconsistently phrased — he used terminology correctly at some points and incorrectly at others, in the specific pattern of someone who had been briefed on a technical subject but had not practised in it professionally.

The visit was ended gracefully. He left. Nair's team followed him. The IB contact was provided the information for further action.

Karan was briefed in a one-page note.

He wrote in the margin: The system works. The document control programme begins now.

The document control system — every technical document in ISMC and Shergill Computer Systems logged in the Chanakya database, every access recorded, every copy tracked — was operational by January 1976.

When Krishnaswami had complained that the system added twenty minutes to every significant technical communication, Karan had said: "What is the cost of the IPL-3 process becoming available to an American semiconductor company?"

Krishnaswami had thought about this.

He had said: "Years of advantage eliminated. The specific number is hard to calculate because it depends on how fast a foreign lab could replicate our process with our specific technical approach versus without it." He paused. "Probably three to five years of process advantage."

"And twenty minutes per communication times the number of significant communications in a year," Karan had said.

Krishnaswami had done the arithmetic.

He had implemented the document control system.

Project Shakti: The Brahma-32 Architecture

Project Shakti — the 32-bit architecture programme — had begun formally in January 1975, running in parallel with the Brahma-16's ongoing production qualification.

Malhotra's architecture team had spent the first four months defining requirements. Not the feature requirements — those came from the applications the processor needed to run. The architecture requirements: what constraints did the Brahma-32's design need to satisfy in order to be a sound foundation for the subsequent 64-bit and 128-bit generations?

This was the question that Karan had forced into the design process from the roadmap meeting in January 1974, and it was the question that most processor architects of the 1970s were not asking, because most processor architects were designing the current generation without explicit consideration of the generations that would follow.

Malhotra had initially resisted the constraint.

He had said, in the January 1975 requirements review: "The 64-bit physical processor requirement — the 64-bit virtual address space in the 32-bit machine — I understand the goal. What I want to understand is the cost."

Karan had said: "Tell me the cost."

Malhotra had said: "The 64-bit virtual address requires a three-level page table structure for the virtual memory management unit. The memory overhead for the page tables — the structure that maps virtual addresses to physical addresses — will be significant on a system running many simultaneous processes. For the Railway booking system's database server, which we are designing as a primary deployment target, with thousands of simultaneously active user sessions, the page table overhead could consume twenty percent of the available physical memory."

Karan had said: "Twenty percent of the current memory configurations or twenty percent of future memory configurations?"

A pause.

"Current memory is expensive," Malhotra had said. "The cost per megabyte will fall over time as the ISMC device manufacturing improves its DRAM yield."

"How much will it fall?" Karan had said.

"I do not know precisely," Malhotra had said. "But the trajectory is consistent: memory costs fall as process technology improves. A processor architecture designed for the memory cost of 1975 will be constrained by a burden that does not exist in 1985."

"So the twenty percent overhead," Karan had said, "is a 1975 problem and not a 1985 problem."

"Yes," Malhotra had said, slowly.

"And the inability to address 64-bit virtual memory without a complete architecture change," Karan had said, "is a 1985 problem and a 1990 problem and a 1995 problem."

Malhotra had been quiet.

He had said: "You are trading a temporary cost for a permanent capability."

"Yes," Karan had said. "That is always the correct trade when the capability is right and the cost is temporary."

The Brahma-32 architecture specification was completed in March 1976 — 450 pages, twice the length of the Brahma-16 specification, covering the virtual memory management with its three-level page table, the two-mode execution model, the extended instruction set, and the floating-point unit that Malhotra had added on his own initiative.

The floating-point unit had not been in Karan's original requirements. Malhotra had added it because the Brahma-32's primary initial applications — scientific computing at ISMC, engineering simulation at Shergill Aeronautics, the Chanakya database's numerical operations — all involved significant floating-point computation, and software emulation of floating-point on 32-bit integer hardware was fifteen to twenty times slower than hardware implementation.

He had brought the addition to Karan as a formal change request rather than implementing it unilaterally.

He had said: "The floating-point unit adds approximately thirty thousand transistors to the die. On the one-micron process, this is feasible. The performance benefit for the target applications is significant. The cost is die area and development time — approximately four months additional architecture work."

Karan had approved it without discussion.

Not because he had not thought about it. Because the thought had already been done: he knew the floating-point unit was correct. The question was whether Malhotra had also understood it was correct and had been willing to bring the change request rather than accepting the original specification as fixed.

The answer was yes.

Good engineers did not accept incorrect specifications. They brought change requests.

The Brahma-32 first silicon, fabricated on the one-micron process from the IPL-3 system, was completed in July 1976.

180,000 transistors. The largest, most complex integrated circuit ever designed or fabricated in India.

Malhotra had spent three days with the validation results before bringing them to Karan.

The results showed: 92 percent validation pass on the first batch. Eight percent failure, all in the floating-point unit's transcendental function hardware — the sine and cosine operations that used an iterative approximation algorithm. The algorithm had a convergence issue for specific input values near the edge of its operational range.

Malhotra had identified the issue, had already designed the correction, and was presenting the first silicon results with the correction plan simultaneously.

He said: "The convergence issue is a software-fixable problem — the firmware that controls the iterative algorithm can be updated to avoid the problematic input range. The hardware correction is cleaner and will be in the revision."

Karan said: "Timeline for the revision."

Malhotra said: "Eight weeks for the revision design. Four weeks for mask revision. Eight weeks to new silicon. Full revalidation in October."

Karan said: "The firmware fix is available when?"

"Two weeks," Malhotra said. "We can ship the Brahma-32 with the firmware fix applied while the hardware revision is in progress. The firmware fix is not ideal — it requires the compiler to avoid generating the specific instruction sequences that trigger the convergence issue — but it is correct. No application will observe the wrong result."

Karan said: "Ship with the firmware fix. Complete the hardware revision in October. Deploy the corrected silicon in November."

"Yes," Malhotra said.

Veda: The Language That Made the Platform

In September 1974, Karan had called Malhotra and Patel to his office — Harish Patel, forty-one, from Ahmedabad, the Software Tools Division's lead, meticulous and clear-thinking, the kind of engineer who made other engineers' work possible by making the tools work correctly.

He had described the problem.

"We are building the Brahma-16, which will be followed by the Brahma-32, which will be followed by the Brahma-64. Every generation of processor is a new architecture. Currently, all systems software is written in assembly language — the language of the specific machine. Assembly language for the Brahma-16 is worthless on the Brahma-32. Every piece of systems software must be completely rewritten with each architecture generation."

Patel said: "This is how all systems software is built. It is the standard."

Karan said: "The standard is expensive and I do not intend to follow it."

He said: "I want a language. Not an assembly language. A language that is close enough to the machine to be used for systems programming — operating systems, compilers, device drivers — but high-level enough that it can be compiled for different processor architectures. So that software written in this language for the Brahma-16 can, with recompilation and modest modification, run on the Brahma-32 and its successors."

He described what the language needed to have: pointer arithmetic, direct memory access, low-level bit manipulation, the ability to call processor instructions the language didn't directly support through an inline assembly mechanism. Control structures that compiled to efficient machine code. A syntax that was readable but compact.

And the most important property: a compiler architecture that was portable. The compiler — the programme that translated the language to machine code — needed to be structured so that the machine-specific portion was small and cleanly separated from the language-processing portion. Porting the compiler to a new architecture meant rewriting only the machine-specific portion.

He described the portability requirement in these terms: when we build the Brahma-32, the compiler port should take four weeks.

Patel looked at him for a moment.

He said: "You are describing a systems programming language that does not yet exist."

"Yes," Karan said.

"The closest thing is BCPL," Patel said. "The language developed at Cambridge. It has some of these properties but not the type system you are describing and not the explicit portability architecture."

"Build better than BCPL," Karan said.

Patel went back to his team.

He assembled the design group: V.K. Ramesh, twenty-eight, exceptional at formal language semantics; Shantanu Rao, thirty-one, who had been writing assembly code for a decade and who understood what systems programmers actually needed from the inside; and Patel himself, who managed the tension between the theoretical requirements and the practical ones.

The language design took ten months. The name Patel gave it was Veda — after the ancient texts, not from nationalistic sentiment but from the engineer's sense that the name should reflect something foundational, something that other things were built on.

The language that emerged was simple by design. Every construct that was not essential had been removed. Every construct that remained had a precise, unambiguous meaning.

Integer types from 8-bit to 32-bit. Character type. Pointer type. Array and structure types. No automatic memory management — the programmer was responsible because only the programmer had sufficient knowledge of the programme's requirements to manage memory correctly in systems contexts. No exception handling. Control structures: if-else, while, for, switch. Function calls. Inline assembly through a well-defined escape mechanism.

The compiler architecture was exactly as Patel had been asked to design it: three phases, the machine-specific phase cleanly separated and small. Front end in 8,000 lines of Veda. Middle end in 6,000 lines. Back end for the Brahma-16 in 4,000 lines.

When Malhotra saw the three-phase architecture he said: "The Brahma-32 port."

Patel said: "New back end. Four thousand lines. Four weeks."

Malhotra said: "That changes the entire platform strategy."

"Yes," Patel said.

Every ISMC systems programme was rewritten in Veda through 1975. The versions were four percent slower than the assembly originals in performance benchmarks. They were sixty percent shorter in code volume and required one-tenth the time to modify when hardware changes required software updates.

The four percent cost was accepted in the first week of the performance comparison. Correctness and maintainability over a platform's lifetime were worth four percent of raw speed. Everyone who had worked on the assembly versions and then worked on the Veda versions understood this immediately, because the difference in working with the two was the difference between working in a medium that resisted you and working in a medium that served you.

The Chanakya-2: Speed as Policy

Rangan's original Chanakya database system had demonstrated what was possible. The Chanakya-2 project was about what was necessary.

The necessity had become clear through scale. The original Chanakya ran adequately on the Brahma-16 for the Gorakhpur facility's internal databases — the component inventory, the engineering document store, the personnel records, the production tracking. For these applications, response times of five to twelve seconds for complex queries were acceptable.

When the Railway Administration proposed extending the Chanakya deployment to the Northern Railway's booking system, the conversation about acceptable response times changed immediately.

Rangan had conducted a user study — not a formal usability test, but a series of conversations with booking clerks at Gorakhpur Junction and the Lucknow Charbagh station, watching them work and timing their transactions. A booking clerk handling a train berth request needed to query availability, confirm the passenger's details, record the booking, and issue the ticket. The total interaction time at the current manual-plus-telephone system was approximately four minutes. A computer system that reduced this to ninety seconds would be valued. A system that reduced it to thirty seconds would transform the workflow. A system where the availability query returned in twelve seconds — in the time it took the clerk to turn to the screen and read the result — would produce a booking rate that was structurally constrained by the query time rather than by the clerk's interaction speed.

Twelve seconds was the Chanakya-1's benchmark query time on the Brahma-16.

Rangan's goal for the Chanakya-2 on the Brahma-32 was under one second.

The architectural change that made this possible was parallel query evaluation.

The original Chanakya query processor evaluated query sub-expressions sequentially. Each sub-expression produced an intermediate result; the intermediate result was passed to the next sub-expression. The work was serial.

The Chanakya-2 query processor identified the sub-expressions that could be evaluated independently — that did not depend on each other's outputs — and evaluated them simultaneously. This required the Brahma-32's superior interrupt handling and memory management, because multiple simultaneously executing query threads needed to access different portions of the database without interfering with each other.

The Brahma-32's hardware virtual memory management was what made this safe: each query thread's memory access was mediated through separate virtual-to-physical mappings, preventing one thread from corrupting another's working data. This was the specific benefit of the virtual memory management unit that Malhotra had designed — the three-level page table that he had initially worried would impose too high a memory overhead. The overhead was real. The benefit was this: the ability to run multiple simultaneous queries correctly, without any possibility of one query corrupting another's results.

The performance result confirmed the design prediction. Queries that had taken twelve seconds on Chanakya-1 returned in under one second on Chanakya-2.

Rangan presented this to Krishnaswami in July 1976 and said: "The architectural implication is larger than the Railway booking application."

Krishnaswami said: "Tell me."

Rangan said: "Any application that requires real-time access to a large, shared database — any application where many users are simultaneously querying and updating shared information — can now be built on the Chanakya-2 architecture. The Northern Railway is one application. The state government's land revenue database is another. The SPEI pharmaceutical distribution tracking is another. The Shikari warranty and service database across the Motor Works dealer network is another."

Krishnaswami said: "You are describing a class of application, not a specific application."

"Yes," Rangan said. "The Chanakya-2 is not a booking system for the Railway. It is a platform for any organisation that needs many people to access and update a large database simultaneously and correctly. The Railway is the first deployment. It should not be the last."

Krishnaswami brought this to Karan.

Karan said: "What is the security architecture for the Railway deployment?"

Krishnaswami looked at him.

Karan said: "The Northern Railway booking database contains the movement records of thirty million passengers per year. It is connected to ticketing terminals across 240 stations. If someone can access any of those terminals, and if the terminal is not protected, they can access the database. If they can access the database, they can read thirty million movement records, or they can corrupt the booking data, or they can write fraudulent bookings."

Krishnaswami said: "These are commercial crime concerns."

Karan said: "They are also intelligence concerns. A database that shows where thirty million people are traveling is a national intelligence resource. If a foreign intelligence service can access it, they know the movement of every political figure who travels by train, every military officer who travels by train, every government official who travels by train." He paused. "Call Nair."

The security architecture meeting with Nair lasted four hours.

The result was a multi-layer protection framework: physical security for all server locations, cryptographic protection of all data in transit between terminals and servers, individual authentication for every terminal operator with session logging, complete audit logging of all database operations, and a redundant backup system capable of restoring the database to its last known correct state within four hours of any detected corruption event.

The cryptographic protection requirement was the most technically demanding. No commercially available encryption hardware existed for this application in India in 1976. The solution was to build it.

ISMC's circuit design team, working from the published technical specifications for the Data Encryption Standard that the American National Bureau of Standards was finalising, designed a hardware encryption circuit on the Brahma fabrication process. The circuit implemented the DES algorithm in hardware, performing encryption and decryption in the time required to transmit the data through the network — adding no perceptible latency to the booking operation.

The key management system — the means by which encryption keys were distributed to terminals and periodically updated — was the final piece. Nair had insisted on physical key distribution rather than electronic distribution: the session keys were generated at a central facility, printed in a machine-readable format, and physically carried to each terminal location by a courier with a specific, documented chain of custody.

This was slow and expensive.

Nair had said, in the meeting where Rangan had proposed electronic key distribution: "Electronic key distribution is faster and cheaper. It is also a second channel through which an adversary can compromise the key material. Physical distribution means the only way to compromise a key is to compromise the specific courier carrying it. The cost is one courier per terminal per key rotation. The benefit is that the cryptographic protection is only as weak as the physical security of the courier."

Rangan had said: "You are designing this as if the adversary is a national intelligence service."

Nair had said: "I am designing this as if the adversary might be. The cost of being wrong in one direction is the cost of physical couriers. The cost of being wrong in the other direction is thirty million movement records in the hands of a foreign intelligence service." He had looked at Rangan. "Which cost do you prefer to accept?"

Physical couriers it was.

The Akash-Net Wide-Area Question

Mehta's Akash-Net Phase 2 — the token-passing ring that had been operating reliably in the Gorakhpur complex for three months — had prompted the natural question.

The question was in a paragraph at the end of his Phase 2 evaluation report.

The Phase 2 Akash-Net connects twelve nodes within a single facility. The natural next question is connecting facilities in different locations — Gorakhpur to Lucknow to Kanpur to Delhi. The same token-passing protocol can operate over longer distances with the appropriate physical medium. Telephone lines can carry the digital signals if properly conditioned. The addressing protocol already supports distinct addressing for thousands of nodes. The technical barriers to a wide-area network are not in the protocol. They are in the physical infrastructure and the regulatory framework. The telephone network is owned by the government. Whether we can use it for data communication is a policy question, not a technical one.

Karan had read this paragraph and written in the margin: This is the question we need to answer. Start the policy work.

He had then spent three evenings thinking about what the wide-area network question actually was.

The technical question was straightforward. A network that connected ISMC in Gorakhpur to the Shergill Aeronautics facility in Nasik to the Shergill Motor Works in Kanpur to the Chanakya-2 server that would serve the Northern Railway — this network would allow the distributed operations of the Shergill enterprise to function as a unified information system rather than as a collection of independent facilities connected by telephone and courier.

The strategic question was different.

A wide-area data network was not a private asset in the way that the Gorakhpur complex's internal Akash-Net was a private asset. The moment the network extended beyond the physical fence of the complex, it used infrastructure — telephone lines, switching equipment, radio spectrum — that the government owned and regulated. Using government infrastructure for data communication required government permission. Government permission created a relationship of dependency. Dependency was the specific thing Karan had been systematically eliminating from every domain of ISMC's operations since 1970.

He thought about this for three evenings.

The resolution he arrived at was not to seek permission to use the telephone network. The resolution was to build the network.

Not the full network — not from Gorakhpur to Delhi to Madras. A demonstration network. Gorakhpur to Lucknow. Ninety kilometres. A dedicated line — not a shared telephone line but a dedicated cable or a dedicated microwave link — that ISMC owned, maintained, and controlled. No dependency on the government's telephone infrastructure. No permission required beyond the right-of-way for a physical cable, which was a construction permit rather than a telecommunications licence.

The dedicated microwave link was the right approach. Microwave radio transmission could carry digital data at high rates over line-of-sight paths, with relay stations at forty-kilometre intervals. The technology was used extensively for long-distance telephone transmission and was well-understood. The ISMC engineering team had built microwave systems as part of the radar development programme for the IAF.

Mehta was given the requirement: design a microwave data link from Gorakhpur to Lucknow, capable of carrying Akash-Net Protocol traffic at sixty kilobits per second, owned and operated entirely by Shergill Industries.

Mehta returned three weeks later with a design.

The design used three relay stations between Gorakhpur and Lucknow, on existing high structures — a television tower, a water tower, an industrial chimney — where Shergill Industries could lease rooftop space for the microwave antennas. The equipment at each relay was ISMC-designed: a receiver, a signal processor that cleaned and rebroadcast the digital signal, and a transmitter. The design was entirely self-sufficient — no foreign components, no government infrastructure, no imported technology.

The construction would take eight months.

Karan approved the project in August 1976.

He had one additional requirement.

He said to Mehta: "The link carries data that is commercially sensitive and may be strategically sensitive as Chanakya-2 deployments extend to government databases. The link must be encrypted end to end. The same hardware encryption that Nair is deploying for the Railway Chanakya-2 implementation."

Mehta said: "The encryption hardware adds latency."

"How much?" Karan said.

"At sixty kilobits per second throughput," Mehta said, "the DES hardware processes data faster than the link transmits it. The latency is below one millisecond. Imperceptible."

"Then encrypt the link," Karan said.

It was the same principle that governed everything in the ISMC security architecture: the cost of adequate protection was almost always lower than the cost of a single serious failure. The discipline was to calculate correctly which cost you were accepting when you made the decision.

The Review: August 21st, 1976

Karan arrived at the Shergill Computer Systems development centre at seven in the morning.

He had scheduled two hours.

He was there for four.

Eleven people: Krishnaswami, Malhotra, Seshadri, Rangan, Patel, Nair, Mehta, Shah, Deshpande, Ramesh, Ghosh.

Ghosh had been added to the standard review list in January 1976. Not because his work had changed — he had been running the optics programme since 1970. Because the IPL-3's entry into production had made the optics programme's output visible in every wafer that came off the fabrication line, and the connection between the lithography work and everything the review covered needed to be explicit.

Ghosh spoke first.

He said: "The IPL-3 is in production. The yield on production wafers is forty-three percent. For a new process at this complexity, forty-three percent is adequate. For commercial scale, sixty percent is the target. I am tracking toward sixty percent by December."

Karan said: "The next generation."

Ghosh said: "The IPL-4. 193-nanometre wavelength. The theoretical resolution limit at 193 nanometres with an NA of 0.6 is 200 nanometres. Production process node at 0.7 to 0.8 microns."

He paused.

He said: "The 193-nanometre light source is the critical problem. The ESU-1 — the krypton-fluoride excimer source that provides the 248-nanometre output for the IPL-3 — can be redesigned for argon-fluoride, which emits at 193 nanometres. The physics of the discharge is similar. The engineering of stable, high-repetition-rate operation at 193 nanometres is harder because argon-fluoride is more reactive and the gas mixture degrades faster."

He looked at Mehta.

Mehta, who had built the ESU-1 and who had been thinking about the ESU-2 since the ESU-1 was completed, said: "The argon-fluoride discharge design is the problem I have been working on since March. The gas management system is the key — a closed-loop gas recycling system that removes the degraded gas components and replenishes them, maintaining the mixture composition within the narrow range required for stable operation." He paused. "I have a design. I need six months to build and test the prototype."

"Six months from January?" Karan said.

"January start, July 1977 prototype," Mehta said.

Karan said: "And the fused silica polishing for the IPL-4 lens."

Ghosh said: "The IPL-3 lens system used fused silica elements polished by Balakrishnan's cerium oxide slurry process. The IPL-4 elements will be polished by the same process, to tighter specifications. Balakrishnan has been testing the tighter specification on IPL-3 spare elements for the past three months. He is confident in the process."

"Good," Karan said.

"The resist chemistry," Ghosh said, looking at Deshpande.

Deshpande said: "The 193-nanometre resist is harder than the 248-nanometre resist. The photoacid generator's absorption spectrum needs to be shifted to match the 193-nanometre photons. This is a significant synthetic chemistry challenge — I am not aware of any published work on photoacid generators with efficient absorption at 193 nanometres."

Karan said: "You have eighteen months before the IPL-4 enters fabrication trial."

Deshpande said: "I need it. I am starting the synthesis programme in September."

"Start in September," Karan said.

He turned to Malhotra.

Malhotra reported on the Brahma-32: first silicon in July, 92 percent validation pass, correction plan underway for the floating-point convergence issue. Production qualification October.

Then he placed a single sheet of paper on the desk.

He said: "The Brahma-64 architecture. The roadmap has it as a 1980 target. With the one-micron process available today, the transistor density is sufficient to build the 64-bit architecture now. The Brahma-64 transistor count — approximately 1.2 million — is achievable on the one-micron process with adequate yield."

Karan said: "Start the architecture work."

Malhotra had been expecting this answer. He had brought the analysis specifically to provoke this answer in this meeting.

He said: "The 64-bit design is fundamentally an extension of the 32-bit design. The same virtual memory model, the same execution modes, the same instruction set semantics, expanded to 64-bit width. The design effort is smaller than either the Brahma-16 or the Brahma-32 because we are extending rather than creating." He paused. "I estimate first silicon in late 1978. Production qualification 1979."

Karan said: "1979 is acceptable." He paused. "The 128-bit research."

Malhotra said: "I want to be honest about what 128-bit means."

"Go ahead," Karan said.

Malhotra said: "A full 128-bit general-purpose processor — 128-bit address space, 128-bit data path throughout — would address a memory space of 340 undecillion bytes. There is no foreseeable application that requires this. The address space alone makes no sense as a design goal." He paused. "But 128-bit arithmetic operations — the ability to perform arithmetic on 128-bit integers in a single instruction — have specific applications: cryptographic operations requiring arithmetic on very large numbers; scientific computing where 64-bit floating-point precision is insufficient."

Nair said, from the end of the table: "RSA encryption requires arithmetic on numbers of at least 1,024 bits for security against anticipated future attack. 128-bit arithmetic operations make RSA implementation approximately eight times faster than 64-bit arithmetic. For a database system encrypting all stored data — the Railway database, any future government database deployments — eight times faster encryption is the difference between acceptable performance and unacceptable overhead."

Malhotra said: "My recommendation: design 128-bit arithmetic operations as an instruction set extension to the 64-bit architecture. Available for the applications that need it, without the overhead of a full 128-bit architecture."

Karan looked at the two of them.

He said: "The cryptographic application is the reason for the 128-bit arithmetic. The security programme is what determines the timeline."

Nair said: "The security programme's timeline is: the Chanakya-2 Railway deployment in 1977, with DES encryption today; the evolution to a stronger cryptographic system as the DES key length proves insufficient in the 1980s." He paused. "The 128-bit arithmetic extension should be ready when the next generation of cryptographic protocols requires it. The 1980 timeframe is appropriate."

Malhotra said: "We design the extension into the Brahma-64 architecture as an optional instruction set capability. Implementation is a separate programme beginning in 1979."

Karan said: "Agreed. Design it in."

He looked at Patel.

Patel reported on the Veda language deployment across all systems software, the Veda-Plus object extension design in progress, and a concern.

He said: "The concern is external disclosure. Veda is the best systems programming language that exists anywhere in the world today. I am not saying this with pride. I am saying it as a technical assessment. Bell Labs in New Jersey is working on a language called C which will eventually be publicly released and will achieve what Veda achieves in a slightly different way. If Veda is published — if Indian universities begin using it — Veda becomes the foundation of Indian software development and gives India's software community a significant advantage in the longer term."

He paused.

He said: "If Veda is not published, we retain the advantage exclusively. But we limit the size of the developer community that can work with ISMC hardware."

Karan said: "Publish Veda under a university licensing arrangement. IIT Bombay and IIT Madras. Non-commercial academic use. Commercial rights remain with Shergill Computer Systems."

He paused.

"But the publication must not include the full compiler source code," he said. "The language specification and a compiled binary compiler are what the universities receive. Not the source code of the compiler itself. The compiler source is the production technology — the implementation knowledge — that we protect."

Patel said: "The universities can use Veda but cannot improve the compiler."

"Not in the short term," Karan said. "In five years, when we have the Brahma-64 compiler and the Veda-Plus compiler and we are sufficiently ahead that the compiler source code is no longer the primary competitive advantage, we revisit. For now: language specification yes, compiler binary yes, source code no."

"I understand," Patel said.

He made the note.

Krishnaswami said: "I want to say something that is not on any agenda item."

Karan looked at him.

Krishnaswami said: "I have been at Bell Labs. I have been at IBM's research laboratory in Zurich. I have been in the most sophisticated semiconductor research environments in the world. I want to be specific about how this team compares."

The room was quiet.

Krishnaswami said: "The Brahma-32 is the most sophisticated processor designed outside North America and Japan. The IPL-3 uses light source technology that does not exist in commercial form anywhere else in the world — the ESU-1 is a novel device. The Veda language is technically comparable to the best systems programming languages being designed anywhere. The Chanakya-2 database is technically comparable to IBM's IMS system, which is the best database system in the world."

He paused.

He said: "None of this was purchased. None of it was licensed. None of it depends on a foreign supplier maintaining their willingness to sell."

He looked at Karan.

"I want to say that clearly," Krishnaswami said. "Because when I was at Bell Labs, the assumption was that Indian technology would always be derivative. That India would always be buying or licensing or imitating. The assumption was comfortable for the people making it. I want to be specific that the assumption was wrong."

The room was quiet for a moment.

Then Karan said: "The intelligence assessment of India's technical capabilities will change sharply in the next three years as these systems become deployed at scale and the performance gap becomes visible. We need to be prepared for what happens when people notice."

Nair said: "The security programme is positioned for this. The physical security, the document control, the personnel security protocols. The one element I want to add is a counter-intelligence capability: active awareness of who is approaching our people and for what purpose. Foreign universities offering fellowships. Commercial partnerships proposed by foreign companies. Academic conference invitations. Each is a potential intelligence gathering opportunity. I want a protocol for evaluating each one."

Karan said: "Build it. I want the protocol by October."

He looked around the room.

He said: "The standard narrative about India's technology development is that we are behind. Catching up. With effort and investment, India can eventually reach the level of the Americans or the Japanese. The standard narrative is about the gap and the time it will take to close it."

He paused.

He said: "That narrative is wrong. It was wrong when I decided to build this facility."

He looked at each person in the room.

He said: "You have built things that do not exist anywhere else. The light source that drives the IPL-3 does not exist as a commercial product in any country. The resist chemistry that makes the one-micron process possible is not published. The Brahma-32's virtual memory architecture is ahead of the Intel 1980 product roadmap. The Veda language is ahead of what Bell Labs will publish in 1979." He paused. "You are not catching up. You are ahead."

He said: "This facility's purpose is not to make India technologically competitive. It is to ensure that India is never in the position of depending on a foreign source for the capabilities that will determine how the second half of the twentieth century develops. Not competitive. Independent. And then, because independence built from first principles and maintained through capability tends to produce genuine advantages — ahead."

He said: "The Cold War is fought in many arenas. In the arena of silicon, the combatants are not yet identified and the battle is not yet joined. When it is joined, the country that can design and manufacture advanced semiconductors from its own tools and its own chemistry and its own architecture will have a strategic capability that cannot be disrupted by export controls or by commercial pressure or by the specific, quiet mechanism by which powerful countries remove the leverage of weaker ones by removing their access to the technology they depend on."

He paused.

"That is what we are building," he said. "Not a technology company. A permanent national capability."

The room was quiet.

Ghosh said, after a moment: "The IPL-4. The 193-nanometre system. If we build it the way we built the IPL-3 — from our own light source, our own optics, our own resist chemistry, our own measurement tools — we will be running a sub-micron process node that no other country has built entirely from domestic capability."

"Yes," Karan said.

"And then the IPL-5," Ghosh said.

"Yes," Karan said.

"There is no point at which we stop," Ghosh said. He said it not as a complaint. As a recognition.

"No," Karan said. "There is not."

Ghosh looked at his hands — the hands that had been polishing optical glass for five years and that had produced the lens system on which everything else in this building depended.

He said: "Then we continue."

"We continue," Karan said.

He looked at the room.

He said: "The IPL-4 programme. The ESU-2 excimer source. The 193-nanometre resist chemistry. The Brahma-64 architecture. The Veda-Plus object model. The Chanakya-2 Railway deployment with full security architecture. The Gorakhpur-Lucknow microwave data link. The 128-bit arithmetic extension design."

He said: "The agenda for the next three years."

He looked at each person.

"Keep building," he said.

He went back to the Lucknow Secretariat.

Outside, the August monsoon was on the fields with its complete, committed attention. Inside the Shergill Computer Systems development centre, eleven engineers went back to their work.

Ghosh sat with the IPL-4 design specification, opened to the section on the 193-nanometre projection optics, and began writing the lens element tolerancing analysis that would tell him, precisely, what Balakrishnan needed to achieve.

Malhotra opened the Brahma-64 specification document to page one and began.

Deshpande went to the synthesis laboratory and began the literature search for 193-nanometre photoacid generators, which was the beginning of the work of designing something that did not exist.

Mehta began the argon-fluoride discharge prototype design.

Patel began drafting the Veda language specification document that would go to IIT Bombay — the specification without the compiler source, the language without the implementation, the science without the production technology.

And in the fabrication facility, the IPL-3 ran — Ghosh's lens system and Deshpande's chemistry and Mehta's excimer source all contributing to the beam of 248-nanometre light that printed patterns one micron wide on silicon wafers, the smallest patterns on the largest chip in India, the product of seven years of work by people who had built everything themselves.

The work was not finished.

The work was never finished.

That was the most important thing about it.

End of Chapter 230

ISMC — Strategic Technology Status, August 1976

Lithography: IPL-3 (indigenous). 248nm DUV, ESU-1 excimer source (indigenous KrF discharge, Mehta), fused silica optics (Ghosh/Balakrishnan cerium oxide polish), acid-catalyzed chemically amplified photoresist (Deshpande formulation). 1-micron production process. No foreign equipment or chemistry. 4-5 years ahead of European/Soviet; 2 years ahead of confirmed Japanese capability. Intel 1980 target reached 1976.

IPL-4 programme authorised: 193nm, ESU-2 ArF excimer source (Mehta, prototype July 1977), sub-micron process target 0.7-0.8 micron.

Processor Architecture: Brahma-16 (production 1973); Brahma-32 (first silicon July 1976, 180K transistors on 1-micron, 92% validation); Brahma-64 (architecture beginning September 1976, first silicon target late 1978); 128-bit arithmetic extension (design into Brahma-64 architecture, implementation programme 1979).

Systems Language: Veda (complete systems programming language, all ISMC software written in Veda, compiler portable to new architecture in 4 weeks). Veda-Plus (object model extension, design 1977). University licensing (specification only, no compiler source).

Database: Chanakya-2 on Brahma-32. Parallel query evaluation: 12s → <1s. Railway deployment 1977. Hardware DES encryption on all network links (indigenous circuit). Physical key distribution.

Network: Akash-Net Phase 2 token ring (12 nodes, 60kbps, deterministic). Gorakhpur-Lucknow microwave data link approved (indigenous design, encrypted, completion 1977).

Security: Full document control (Chanakya-logged), physical security, technical threat modelling, foreign approach evaluation protocol (completion October 1976). No foreign equipment dependency at any layer.